1. Field of the Invention
The present invention relates to a voltage generating circuit.
2. Description of the Related Art
In general, in an internal voltage generating circuit for generating an internal power source voltage V.sub.int in an integrated circuit (IC) etc., a reference voltage is generated by using for example a band gap reference power source, the internal power source voltage V.sub.int generated by the internal voltage generating circuit and the reference voltage are compared, and the internal power source voltage V.sub.int is controlled in response to the result of the comparison.
FIG. 1 is a circuit diagram of an example of a general voltage generating circuit.
As illustrated, the voltage generating circuit of the present example is constituted by a current source I.sub.ext, a band gap reference voltage source V.sub.B, buffers BUF.sub.1 and BUF.sub.2, and a p-type MOS transistor (hereinafter referred to as a pMOS transistor) PT.sub.1.
A reference voltage V.sub.ref, for example a constant voltage of 1.4 V, is generated from the band gap reference voltage source V.sub.B and input to an input terminal "+" of the buffer BUF.sub.1. An inverting input terminal "-" of the buffer BUF.sub.1 is connected to an output terminal, that is, the buffer BUF.sub.1 forms a voltage follower. For this reason, a voltage signal V.sub.BI following the reference voltage V.sub.ref is output to the output terminal of the buffer BUF.sub.1.
The voltage signal V.sub.BI output by the buffer BUF.sub.1 is input to the inverting input terminal "-" of the buffer BUF.sub.2, while the input terminal "+" of the buffer BUF.sub.2 is connected to an output terminal T.sub.vin of the internal power source voltage V.sub.int, therefore the internal power source voltage V.sub.int is supplied to the input terminal "+".
The output terminal of the buffer BUF.sub.2 is connected to a gate of the pMOS transistor PT.sub.1, a source electrode of the pMOS transistor PT.sub.1 is connected to a supply line of the external power source voltage V.sub.ext, and a drain electrode is connected to the output terminal T.sub.vin of the internal power source voltage V.sub.int.
In the voltage generating circuit formed in this way, the voltage signal V.sub.BI output to the output terminal of the buffer BUF.sub.1 from the buffer BUF.sub.2 and the internal power source voltage V.sub.int are compared, and the level of the internal power source voltage V.sub.int is controlled in response to the result of the comparison.
For example, when the internal power source voltage V.sub.int has become higher than the voltage signal V.sub.BI, the output voltage V.sub.B2 of the buffer BUF.sub.2 rises, an ON resistance value of the pMOS transistor PT.sub.1 becomes large in response to this, and the potential of the drain electrode of the pMOS transistor PT.sub.2, that is, the internal power source voltage V.sub.int, is controlled in the downward direction.
On the other hand, when the internal power source voltage V.sub.int has become lower than the voltage signal V.sub.BI, the output voltage V.sub.B2 of the buffer BUF.sub.2 is lowered, the ON resistance value of the pMOS transistor PT.sub.1 becomes small, and the internal power source voltage V.sub.int is controlled in the upward direction.
In this way, the buffer BUF.sub.2 and the pMOS transistor PT.sub.1 always act so as to cancel out the fluctuation of the internal power source voltage V.sub.int, so the internal power source voltage V.sub.int is held at the level of the reference voltage V.sub.ref set by the band gate preference voltage source V.sub.B.
In the above conventional internal voltage generating circuit, however, the reference voltage V.sub.ref generated by the band gap reference power source and the threshold voltage V.sub.th of the pMOS transistor PT.sub.1 have a negative temperature coefficient, so there is a problem that the internal power source voltage V.sub.int is lowered in response to the rise of the temperature.
Further, in an LSI circuit, the mean free path of the carriers is lowered along with a rise of the temperature, therefore the higher the temperature, the lower the speed of the LSI circuit. This is superposed on the reduction of the internal power source voltage V.sub.int due to the temperature characteristic, so a large design margin is necessary.